Encore SIM EDITOR SOFTWARE Guide de l'utilisateur Page 47
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
1-1
Getting Started
1
Getting Started 1
VCS
®
is a high-performance, high-capacity Verilog
®
simulator that
incorporates advanced, high-level abstraction verification
technologies into a single open native platform.
VCS enables you to analyze, compile, and simulate Verilog design
descriptions. It also provides you with a set of simulation and
debugging features to validate your design. These features provide
capabilities for source-level debugging and simulation result viewing.
VCS supports all levels of design descriptions, but is optimized for
the behavioral and register transfer levels.
VCS accelerates complete system verification by delivering the
fastest and highest capacity Verilog simulation for RTL functional
verification.
In addition, VCS supports Synopsys DesignWare IP, the VCS
Verification Library, VMC models, and the Vera testbench tool.
- User Guide 1
- Contents 3
- Getting Started 1 47
- Getting Started 48
- What VCS Supports 49
- Main Components of VCS 49
- Preparing to Run VCS 52
- Obtaining a License 53
- Setting Up Your Environment 54
- Setting Up Your C Compiler 55
- VCS Workflow 56
- Coverage Metrics User Guide 57
- % vcs mem.v cpu.v 58
- Basic Compile-Time Options 60
- Running a Simulation 64
- Basic Runtime Options 65
- Modeling Your Design 1 69
- Avoiding Race Conditions 70
- Flip-Flop Race Condition 72
- Counting Events 74
- Time Zero Race Conditions 75
- Conditional Compilation 77
- Combining the Techniques 81
- and more 91
- Case Statement Behavior 92
- Memory Size Limits in VCS 93
- Using Sparse Memory Models 93
- Obtaining Scope Information 95
- Modeling Your Design 100
- Avoiding Circular Dependency 101
- Dealing With Unassigned Nets 103
- Code Values at Time 0 104
- Signal Value/Strength Codes 106
- Compiling Your Design 1 109
- Using the vcs Command 110
- Incremental Compilation 111
- Triggering Recompilation 112
- Using Lint 118
- +lint=GCWM,NCEID 119
- +lint=none 120
- Enabling the Checking 123
- Filtering Out False Negatives 124
- HSOPT Technology 126
- Condition 128
- +cliecho +no_pulse_msg 129
- +sdverbose +vcs+finish 129
- Performance Considerations 131
- Compilation 136
- Doing SDF annotation 137
- Minimizing Memory Consumption 138
- Memory Setup 140
- /usr/ccs/bin/sparcv9/ld 141
- Using Radiant Technology 142
- Known Limitations 143
- The Configuration File Syntax 145
- Radiant Technology 151
- Library Mapping Files 153
- Displaying Library Matching 155
- Configurations 156
- Configuration Syntax 157
- Hierarchical Configurations 159
- The -top Compile-Time Option 160
- Limitations of Configurations 161
- Simulating Your Design 1 163
- % executable [options] 164
- Simulating Your Design 165
- Save and Restart 166
- Save and Restart File I/O 168
- Simulation 170
- Improving Performance 174
- Profiling the Simulation 175
- CPU Time Views 176
- “Moduletime” 181
- Memory Usage Views 186
- The Program View 189
- Example 4-12 Program View 189
- DVE Panes 194
- Managing DVE Windows 194
- Setting Display Preferences 200
- VPD and EVCD File Generation 209
- Advantages of VPD 210
- $vcdplusoff 212
- $vcdplusoff(test.risc1.alu1); 213
- $vcdplusflush; 213
- $vcdplusautoflushon 214
- $vcdplusautoflushoff 214
- Syntax for Specifying MDAs 215
- Note: Unlimited dimensions 219
- $vcdplusmemon( mem01 ); 220
- Starting bound: 221
- Ending bound: 221
- Example 6-6 Selected element: 225
- Using $vcdplusmemorydump 226
- Execution Data 227
- Execution 228
- Source Statement System Tasks 229
- $vcdplustraceon 229
- $vcdplusdeltacycleon; 230
- $vcdplusdeltacycleoff; 231
- $vcdplusglitchon; 231
- $vcdplusglitchoff; 232
- Runtime Options 233
- +vpdbufsize+nn 234
- +vpdfile+filename 234
- +vpdfilesize+nn 235
- +vpdignore 235
- +vpddrivers 236
- +vpdnoports 236
- +vpdnocompress 236
- VPD Methodology 237
- VPD On/Off PLI Rules 240
- Performance Tips 241
- EVCD File Generation 243
- VCD and VPD File Utilities 1 245
- The vcdpost Utility 246
- " out1 [6] $end 247
- The vcdpost Utility Syntax 248
- The vcdiff Utility 249
- The vcdiff Utility Syntax 250
- VCD and VPD File Utilities 251
- The vcat Utility 256
- The vcat Utility Syntax 257
- 10000 x 258
- 30 z 258
- The vcsplit Utility 267
- The vcd2vpd Utility 270
- The vpd2vcd Utility 272
- The Command file Syntax 274
- The vpdmerge Utility 277
- Restrictions 279
- Value Conflicts 280
- Using UCLI 285
- UCLI Interactive Commands 286
- UCLI Command-Alias File 291
- Operating System Commands 291
- CLI Commands 294
- For example: 298
- Traversing Call-stacks 301
- Command Files 303
- Key Files 305
- Post-Processing 2 317
- Post-Processing 318
- Line Tracing 319
- Delta Cycle 319
- Race Detection 1 321
- Race Detection 322
- Enabling Race Detection 324
- Conditions 325
- The Race Detection Report 325
- END RACE REPORT 326
- Post Processing the Report 328
- #! /usr/local/bin/perl 330
- Delays and Timing 1 335
- Transport and Inertial Delays 336
- Delays and Timing 337
- Pulse Control 341
- +pulse_e/0 +pulse_r/0 347
- Specifying the Delay Mode 354
- SDF Backannotation 1 357
- Using SDF Files 358
- The $sdf_annotate System Task 359
- SDF Backannotation 360
- Precompiling an SDF File 363
- The SDF Configuration File 372
- Delay Objects and Constructs 373
- MTM=MAXIMUM; 376
- 379
- Example: 381
- DEVICE (1:2:3) 385
- (INSTANCE CELLTYPE) 387
- (ABSOLUTE 387
- (DEVICE B (1:2:3)) 387
- INTERCONNECT Delays 388
- Min:Typ:Max Delays 393
- +timopt+100ns 396
- DONE TIMOPT 397
- Editing the timopt.cfg File 399
- Editing Clock Signal Entries 400
- Negative Timing Checks 1 401
- Negative Timing Checks 402
- reg clk, d; 414
- reg rst; 414
- wire q; 414
- Checking Conditions 418
- How VCS Calculates Delays 420
- So the timing checks are now: 425
- Timing violation in top.fd1_1 427
- SAIF Support 2 429
- Using SAIF Files 430
- SAIF System Tasks 430
- $toggle_start(); 431
- $toggle_stop(); 431
- $toggle_reset(); 431
- "rtl_on" 432
- "off" 432
- "on" 432
- System Tasks 433
- SAIF Support 434
- SWIFT Environment Variables 438
- ${LD_LIBRARY_PATH} 439
- Generating Verilog Templates 440
- Using the PLI 2 453
- Using the PLI 454
- Writing a PLI Application 455
- The PLI Table File 458
- ACC_capabilities 460
- PLI Specifications 461
- ACC Capabilities 463
- or read 465
- or read_write 465
- or callback 465
- ‘celldefine compiler 467
- -y and -v compile-time 467
- Features 469
- or force 471
- Using the PLI Table File 472
- Enabling ACC Capabilities 473
- Configuration File 474
- {accWrite}; 475
- +applylearn+filename 479
- Using VPI Routines 481
- DirectC Interface 3 489
- DirectC Interface 490
- Declaring the C/C++ Function 494
- Calling the C/C++ Function 500
- Converting Strings 505
- Avoiding a Naming Problem 507
- Using Direct Access 508
- Using the vc_hdrs.h File 515
- Using Abstract Access 517
- Using vc_handle 518
- Using Access Routines 519
- ’b’, ’o’, ’d’, or ’x’ 531
- This example now displays: 532
- The C code is as follows: 537
- Same as vc_toInteger 537
- U *vc_2stVectorRef(vc_handle) 539
- UB *vc_MemoryRef(vc_handle) 544
- memcpy(p2,p1,8); 545
- p2 += 8; 545
- } 545
- #define scalar_0 0 560
- #define scalar_1 1 560
- #define scalar_z 2 560
- #define scalar_x 3 560
- U vc_mdaSize(vc_handle, U) 564
- 565
- Summary of Access Routines 565
- Enabling C/C++ Functions 569
- Specifying the DirectC.h File 571
- Useful Compile-Time Options 572
- Environment Variables 573
- Interface 1 577
- Usage Scenario Overview 580
- Supported Port Data Types 581
- Input Files Required 583
- The Verilog model is display: 587
- Using GNU Compilers on Linux 591
- Generating the Wrapper 593
- Instantiating the Wrapper 595
- Elaborating the Design 597
- Use a Stubs File 599
- Using a Port Mapping File 602
- Debugging the Verilog Code 605
- Transaction Level Interface 607
- Interface Definition File 609
- Transaction Debug Output 613
- Instantiation and Binding 614
- Miscellaneous 618
- Using OpenVera Assertions 1 623
- Introducing OVA 624
- Using OVA Directives 625
- Using OpenVera Assertions 626
- OVA Flow 629
- Linter General Rule Messages 631
- Linter General Rule Messages: 638
- OVA Runtime Options 643
- OVAPP Flow 647
- [-ova_dir directory_path] 648
- Directory 654
- Viewing Output Results 663
- Using the Default Report 664
- Command Line Options 667
- Inlining OVA in Verilog 670
- Specifying Pragmas in Verilog 671
- Methods for Inlining OVA 672
- //ova_begin 674
- //OVA_END 674
- //ova bind 675
- //ova [(port1, ..., portN)]; 675
- Checker Library 678
- Case Checking 681
- // ova parallel_case; 682
- // ova full_case; 682
- // ova no_case; 682
- Use Model 685
- Limitations on the Input 686
- Recommended Methodology 688
- Caveats 688
- Post-processing Flow 689
- Global Monitoring 692
- Name-Based Monitoring 695
- (category, action); 696
- Task Invocation From the CLI 698
- Debug Control Tasks 699
- Calls From Within Code 700
- $ova_stop system task: 701
- $ova_severity_action: 703
- OpenVera Native Testbench 1 707
- OpenVera Native Testbench 708
- OpenVera 709
- Other Features 710
- Preprocessor Directives 712
- Top Level Constructs 713
- Program Block 713
- "Hello World!" 714
- The Template Generator 715
- Multiple Program Support 717
- Compiling Multiple Programs 719
- Example Configuration File 725
- Multiple program example: 726
- [ntb_compile-time_options] 730
- % simv +vcs_runtime_options 730
- -ntb_shell_only] tb.vr 732
- Top-level Verilog Module 733
- % simv +ntb_load=./libtb.so 734
- Compile-time Options 735
- -ntb_filext .vr 737
- -ntb_filext .vr+.vri+.vrl 737
- -ntb_incdir ../src1 737
- Value Description 744
- Reordering 747
- Circular Dependencies 749
- Encryption 749
- Using Encrypted Files 750
- Testbench Functional Coverage 751
- Measuring Coverage 755
- -cg_coverage_control=value 757
- Example 21-2 758
- Coverage Reporting Flow 760
- Mozilla): 761
- Solver Choice 767
- Temporal Assertions 769
- Temporal Assertion Flow 771
- Including the Header Files 772
- Resetting Assertion 773
- Suspending Threads 776
- Terminating the AssertEngine 777
- Example Testbench 777
- Together 781
- Scope of Interoperability 782
- Data Type Mapping 786
- Mailboxes and Semaphores 787
- Strings 789
- Enumerated Types 789
- Integers and Bit-Vectors 792
- Structs and Unions 794
- Connecting to the Design 795
- Miscellaneous Issues 800
- Constructs 800
- Functional Coverage 801
- Testbench Optimization 805
- Enabling the NTB Profiler 806
- Performance Profiler Example 806
- Example 21-11 dpi.c 807
- Compile: 808
- 0.84% of the total time 810
- VCS Memory Profiler 811
- Note: 817
- VCS Memory Profiler Output 818
- SystemVerilog Data Types 822
- The chandle Data Type 823
- User-Defined Data Types 825
- Enumerations 825
- Methods for Enumerations 826
- The $typeof System Function 828
- Structures and Unions 830
- Structure Expressions 833
- SystemVerilog Arrays 834
- Multiple Dimensions 835
- Indexing and Slicing Arrays 836
- Programs 838
- Writing To Variables 839
- Automatic Variables 841
- Multiple Drivers 842
- Release Behavior 843
- Integer Data Types 844
- Unpacked Arrays 846
- Structures 847
- Using the VPI 848
- SystemVerilog Operators 850
- New Procedural Statements 851
- Statements 852
- The do while Statement 854
- SystemVerilog Processes 855
- The always_latch Block 858
- The always_ff Block 858
- Tasks and Functions 859
- Functions 861
- SystemVerilog Packages 866
- SystemVerilog DPI 870
- #5 i = i/2; 872
- endtask 872
- Hierarchy 874
- New Data Types for Ports 876
- Ref Ports on Modules 880
- Encapsulation 882
- Example 22-5 Basic Interface 884
- Using Modports 886
- Functions In Interfaces 888
- Enabling SystemVerilog 889
- Immediate Assertions 892
- Sequences 893
- Using Repetition 896
- Specifying a Clock 899
- Value Change Functions 899
- Anding Sequences 900
- Oring Sequences 901
- Conditions for Sequences 902
- Sequence 903
- Properties 907
- Inverting a Property 911
- Past Value Function 912
- The disable iff Construct 912
- Action Blocks 918
- The VPI For SVA 922
- -ova_debug -ova_dir -ova_file 930
- -ova_cov_name -ova_cov_db 931
- The report.index.html File 947
- The tests.html File 952
- The category.html File 952
- The hier.html File 953
- Assertion System Functions 958
- Using Assertion Categories 958
- Using Attributes 960
- VCS Flow for SVTB 967
- Testbench Constructs 968
- -cm_name filename 970
- The string Data Type 971
- String Conversion Methods 974
- Predefined String Methods 978
- Program Blocks 981
- Dynamic Arrays 986
- The new[ ] Built-In Function 986
- The size() Method 988
- The delete() Method 988
- Associative Arrays 990
- Wildcard Indexes 991
- String Indexes 991
- Associative Array Methods 992
- VCS displays the following: 994
- Queue Methods 997
- The foreach Loop 1000
- Constraints 1003
- List of Aggregate Methods 1004
- Table 24-1 1004
- Constructors 1008
- Static Properties 1011
- Class Extensions 1015
- Abstract classes 1016
- Polymorphism 1018
- The Output of the program is: 1020
- Chaining Constructors 1024
- Accessing Class Members 1028
- Methods 1029
- “this” keyword 1030
- Class Packet Example 1032
- Random Constraints 1034
- Constraint Blocks 1035
- External Declaration 1038
- Inheritance 1038
- Set Membership 1039
- Weighted Distribution 1041
- Implications 1042
- Global Constraints 1045
- Default Constraints 1046
- Variable Ordering 1053
- Unidirectional Constraints 1054
- Constraint Early Late 1059
- Static Constraint Blocks 1065
- Randomize Methods 1066
- Controlling Constraints 1068
- Disabling Random Variables 1071
- Output of the above program: 1073
- In-line Constraints 1074
- In-line Constraint Checker 1075
- Random Number Generation 1077
- $srandom() 1079
- Seeding for Randomization 1081
- Random Sequence Generation 1083
- RSG Overview 1084
- Production Declaration 1085
- Production Controls 1088
- Weights for Randomization 1088
- Aspect Oriented Extensions 1094
- Element Description 1104
- Precedence 1109
- Example 24-14 1116
- Example 24-16 1119
- Point 1: Value = 5 1123
- Point 2: Value = 5 1123
- Point 3: Value = 6 1123
- Output is: 6 1123
- Examples 1126
- Examples of advice code 1128
- Example 24-23 : 1128
- Example 24-26 1130
- Array manipulation methods 1131
- Array locator methods 1133
- Array reduction methods 1139
- Semaphores 1143
- Semaphore Methods 1145
- Mailboxes 1146
- Mailbox Methods 1148
- Waiting for an Event 1149
- Persistent Trigger 1150
- Merging Events 1151
- Reclaiming Named Events 1152
- Event Comparison 1153
- Clocking Blocks 1154
- input #0 i1; 1156
- `timescale 1ns/1ns 1157
- Input and Output Skews 1159
- Hierarchical Expressions 1160
- Clocking Block Events 1162
- Default Clocking Blocks 1162
- Cycle Delays 1163
- Input Sampling 1164
- Synchronous Events 1165
- Synchronous Drives 1165
- Drive Value Resolution 1166
- Virtual Interfaces 1173
- Scope of Support 1174
- Virtual Interface Modports 1174
- Array of Virtual Interface 1177
- Clocking Block 1178
- Event Expression/Structure 1179
- Null Comparison 1179
- Coverage 1180
- The covergroup Construct 1181
- Defining a Coverage Point 1183
- Bins for Value Ranges 1183
- Bins for Value Transitions 1187
- Defining Cross Coverage 1189
- Defining Cross Coverage Bins 1190
- Cumulative Coverage 1192
- Instance-based Coverage 1193
- Coverage Options 1193
- Predefined Coverage Methods 1196
- Output of the program is: 1200
- Unified Coverage Reporting 1203
- The Coverage Report 1204
- The ASCII Text File 1204
- The HTML File 1206
- Post-Processing Tools 1207
- Test Name Database 1208
- Loading Coverage Data 1209
- -cm_dir and -cm_name will 1211
- -cm_dir directory_path_name 1211
- VCS NTB (SV) Memory Profiler 1212
- UCLI Interface 1213
- CLI Interface 1213
- Incremental Profiling 1214
- Only Active Memory Reported 1214
- Declaration : 1217
- Limitations 1219
- Include Files 1219
- SystemVerilog File 1222
- Source Protection 1 1223
- Source Protection 1224
- Encrypting Source Files 1225
- Encrypting Specified Regions 1226
- option: 1229
- Encrypting SDF Files 1231
- Simulating Encrypted Models 1234
- Using System Tasks 1235
- Writing PLI Applications 1235
- Mangling Source Files 1236
- -Xmangle=4 option: 1239
- -Xmangle=12 option: 1240
- -Xmangle=28 option: 1242
- Creating A Test Case 1245
- [, module_identifier...] 1246
- VCS Environment Variables A 1249
- VCS Environment Variables 1250
- VCS_LIC_EXPIRE_WARNING 5 1252
- VCS_LIC_EXPIRE_WARNING 0 1252
- Compile-Time Options B 1253
- % vcs top.v toil.v +v2k 1254
- Compile-Time Options 1255
- Options for SystemVerilog 1261
- .SystemClock (SystemClock) 1265
- .adder_inp1 (inp1) 1265
- .adder_inp2 (inp2) 1265
- Options for Debugging 1269
- -cm line+cond+fsm+tgl 1276
- -cm_cond basic+allops 1277
- +vcdfile+filename 1283
- -f -gen_asm -gen_obj 1290
- -line -l -u -v -y 1290
- Executable 1291
- Options for Pulse Filtering 1292
- Options for PLI Applications 1293
- Timing Checks 1294
- SmartModels 1297
- +lint=[no]ID 1298
- +warn=[no]ID 1299
- Options for Cell Definition 1300
- Options for Licensing 1301
- -cc compiler 1303
- -CC options 1303
- Options for Source Protection 1306
- General Options 1310
- Enable Verilog 2001 Features 1310
- Reduce Memory Consumption 1310
- TetraMAX 1311
- Specifying a VCD File 1311
- Specifying a Log File 1312
- Hardware Modeling 1313
- Defining a Text Macro 1313
- For Long Calls 1314
- Simulation Options C 1317
- Simulation Options 1318
- Options for Coverage Metrics 1326
- Options for Recording Output 1329
- +sdfverbose 1330
- Options for VPD Files 1331
- Operations 1334
- Options for VCD Files 1334
- MIPD Annotation 1339
- This appendix describes: 1341
- • Compiler Directives 1341
- • System Tasks and Functions 1341
- Compiler Directives 1342
- General Compiler Directives 1348
- System Tasks and Functions 1350
- System Tasks for VCD Files 1352
- System Tasks for VPD Files 1358
- Commands 1367
- System Tasks for Log Files 1367
- System Tasks for File I/O 1369
- System Tasks for Time Scale 1372
- System Tasks for PLA Modeling 1376
- Checks for a Plusarg 1379
- SDF Files 1379
- Counting the Drivers on a Net 1380
- Depositing Values 1380
- PLI Access Routines E 1383
- PLI Access Routines 1384
- Parameter Value 1421
- 1426
- *filename) 1429
- int tag) 1437
- No return value 1438
- VCS API Routines 1467
- $fseek D-30 1471
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