Encore SIM EDITOR SOFTWARE Guide de l'utilisateur télécharger pdf (Page 70)

2-2

Modeling Your Design

• Memory Size Limits in VCS

• Using Sparse Memory Models

• Obtaining Scope Information

• Avoiding Circular Dependency

• Designing With $lsi_dumpports for Simulation and Test

Avoiding Race Conditions

A race condition is defined as a coding style for which there is more

than one correct result. Since the output of the race condition is

unpredictable, it can cause unexpected problems during simulation.

It is easy to accidentally code race conditions in Verilog. For example,

in Digital Design with Verilog HDL by Sternheim, Singh, and Trivedi,

at least two of the examples provided with the book (adder and

cachemem) have race conditions. VCS provides some tools for race

detection. For details, see Chapter 11, "Race Detection".

Some common race conditions and ways of avoiding them are

described in the following sections.

Using and Setting a Value at the Same Time

In this example, the two parallel blocks have no guaranteed ordering,

so it is ambiguous whether the $display statement will be executed.

module race;

reg a;

initial begin

a = 0;

#10 a = 1;

1 2 ... 65 66 67 68 69 70 71 72 73 74 75 ... 148 149

Pas de commentaire

Encore SIM EDITOR SOFTWARE Guide de l'utilisateur Page 70